Different rendering machines and displays at the endpoints of IP networks can show different end-to-end latencies.
A typical chain consists of the following components:                (1) Source        (2) Encoder        (3) Network        (4) Decoder        (5) Renderer        (6) Display        
Each hardware and/or software component in such a chain can in general have different processing time periods (processing latency) and these processing time periods can vary over time. Also the applied hardware and/or software solutions are evolving over time, and consequently the processing time periods can change. Also the network has in general a different delay to the different endpoints, and also this delay can vary over time (network latency).
Solutions for re-synchronizing data streams from the source to the destination are possible, for example as disclosed in RFC 3550, as long as the data can be controlled within a data processing framework and with high precision (e.g. <150 ms).
Typically, the last synchronization point can be either just after the decoding (in the case of a software decoder) or just before the decoding (in the case of a hardware decoder). As such, the decoding, rendering and displaying add an unknown amount of latency that in general can be different between the different endpoints. This latency can in general be different for the various endpoints because the latency depends on the specific hardware and/or software implementations. Moreover this latency can vary over time for each endpoint.
Many applications require that the displayed images at the different endpoints are “data-synchronized” i.e. the displays must display the same frame at the same point in time. It is therefore important that the different end-to-end latencies can be measured in an easy way and compensated accordingly. Such a recalibration is necessary on a regular basis because the end-to-end latency for the various endpoints can change over time.
In U.S. Pat. No. 4,540,982 the delay compensation is realized in hardware with flip-flops and AND-gates to implement multi-vibrator circuits. In essence a differential clock generator i.e. two clock trains, of the same frequency is implemented, that can be relative phase shifted. The two shifted clocks are used to compensate for all kinds of delays in electronic circuits.
In US 2007/0247470 A1 a solution is described to reduce the latency of a display device. A controller controls the transfer of pixels from a frame buffer to the display module. The controller monitors the content of the frame memory. A minimum number of pixels must be available in the buffer memory before the transfer to the display module starts. This minimum number of pixels depends on the image format (e.g. number of lines and the refresh rate). In this solution the controller is not waiting till a full frame is available in the frame memory but starts to transfer the pixels from the frame memory earlier to reduce the latency caused by the display device.